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TSM1285 page 1 ? 2014 silicon laboratories, inc. all rights reserved. features ? alternate source for max1285 and higher-speed upgrade to max1240 and max1241 ? single-supply operation: +2.7v to +3.6v ? dnl & inl: 1lsb (max) ? 300ksps sampling rate ? low conversion-mode supply current: 2.5ma @ 300ksps ? low supply current in shutdown: 2a ? internal track-and-hold ? internal +2.5v reference ? spi ? /qspi?/microwire? 3-wire serial- interface 1 ? 8-pin soic package applications process control and factory automation data and low-frequency signal acquisition portable data logging pen digitizers & tablet computers medical instrumentation battery-powered instruments 1 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. description the TSM1285 ? a single-supply, single-channel, 12- bit analog-to-digital converte r (adc) - is an alternate source for the max1285 and a higher-speed upgrade to the max1240 and max1240 adcs. the TSM1285 combines a high-bandwidth track-and-hold (t/h), a high-speed serial digital interface, an internal +2.5v reference, and low conversion-mode power consumption. the TSM1285 operates from a single +2.7v to+3.6v supply and draws less than 2.5ma at 300ksps. connecting directly to any spi, qspi, microwire? microcontrollers and other interface-compatible computing devices, the TSM1285?s 3-wire serial interface is easy to use and doesn?t require separate, external logic. an exter nal serial-interface clock controls the TSM1285?s conv ersion process and its output shift register operation. in pcb-space-conscious, low-power remote-sensor and data-acquisition applications, the TSM1285 is an excellent choice for its low-power, ease-of-use, and small-package-footprint attributes. the TSM1285bc is fully specified over the 0c to +70c temperature range. TSM1285be is fully specified over the -40c to +85c temperature range. both products are available in a 8-pin soic package. a 300ksps, single-supply, low-power 12-bit serial-output adc functional block diagram
TSM1285 page 2 TSM1285 rev. 1.0 absolute maximum ratings v dd to gnd.................................................................... -0.3v to +6v ain to gnd ...................................................... -0.3v to (v dd + 0.3v) ref to gnd ..................................................... -0.3v to (v dd + 0.3v) digital inputs to gnd ....................................... -0.3v to (v dd + 0.3v) dout to gnd .................................................. -0.3v to (v dd + 0.3v) dout current ........................................................................ 25ma continuous power dissipation (t a = +70c): 8-pin soic (derate 5.88mw/c above +70c) .............. 471mw operating temperature ranges: TSM1285bc ........................................................... 0c to +70c TSM1285be ....................................................... -40c to +85c storage temperature range .................................. -60c to +150c lead temperature (soldering, 10s) ....................................... +300c soldering temperature (reflow) ........................................... +260c electrical and thermal stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the op erational sections of the specifications is not implied. ex posure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. package/ordering information order number part marking temperature range carrier quantity TSM1285bcsa+ t1285b 0oc to 70oc tube 97 TSM1285bcsa+t tape & reel 2500 TSM1285besa+ t1285be -40oc to +85oc tube 97 TSM1285besa+t tape & reel 2500 lead-free program: silicon labs supplies only lead-free packaging. consult silicon labs for produ cts specified with wider oper ating temperature ranges.
TSM1285 TSM1285 rev. 1.0 page 3 electrical specifications v dd = +2.7v to +3.6v; f sclk = 4.8mhz, 50% duty cycle, 16 cloc ks/conversion cycle, 300ksps; 4.7 f capacitor at ref; t a = -40oc to +85oc, unless otherwise noted. typical values apply at t a = +25c. parameter symbol conditions min typ max units dc accuracy (see note 1) resolution 12 bits relative accuracy inl see note 2 1.0 lsb differential nonlinearity dnl no missing c odes over temperature 1.0 lsb offset error ze 6.0 lsb gain error ge see note 3 6.0 lsb gain-error temperature coefficient tcge 1.6 ppm/c dynamic specifications (f in = 75khz sine wave, 2.5v pp , f sample = 300ksps, f sclk = 4.8mhz) signal-to-noise plus distortion ratio sinad 70 db total harmonic distortion thd including the 5th harmonic -80 db spurious-free dynamic range sfdr 80 db intermodulation distortion imd f a = 73khz, f b = 77khz 76 db full-power bandwidth fpbw -3db point 3 mhz full-linear bandwidth flbw sinad > 68db 250 khz conversion rate conversion time t conv see note 4 3.3 s track/hold acquisition time t a cq 625 ns aperture delay t a d 10 ns aperture jitter t a j < 50 ps serial clock frequency t sclk 0.5 4.8 mhz duty cycle 40 60 % analog input (ain) input voltage range v in 0 2.5 v input capacitance c in a 10 pf internal reference ref output voltage vref 2.48 2.50 2.52 v ref short-circuit current t a = +25c 15 ma ref output tempco tcvref 15 ppm/c load regulation see note 5; 0 to 0.75ma output load 0.1 2.0 mv/ma capacitive bypass at ref 4.7 10 f digital inputs (sclk, cs , shdn ) input high voltage v inh 2.0 v input low voltage v inl 0.8 v input hysteresis v hyst 0.2 v input leakage i in v inl = 0v or v inh = v dd 1 a input capacitance c ind 15 pf digital output (dout) output voltage low v ol i sink = 5ma 0.4 v output voltage high v oh i source = 0.5ma v dd - 0.5 v three-state leakage current i l v cs = +3v 10 a three-state output capacitance c out v cs = +3v 15 pf power supply positive supply voltage v dd see note 6 2.7 3.6 v positive supply current i dd see note 7; v dd = +3.6v 2.5 3.5 ma shutdown supply current i shdn sclk = v dd , shdn = gnd 2 10 a power-supply rejection psr v dd = +2.7v to 3.6v, midscale input 0.5 mv
TSM1285 page 4 TSM1285 rev. 1.0 timing specifications v dd = +2.7v to +3.6v, t a = -40oc to +85oc, unless otherwise noted. parameter symbol conditions min typ max units sclk period t cp 208 ns sclk pulse-width high t ch 83 ns sclk pulse-width low t cl 83 ns cs fall to sclk rise setup t css 45 ns sclk rise to cs rise hold t csh 0 ns sclk rise to cs fall ignore t cso 45 ns cs rise to sclk rise ignore t cs1 45 ns sclk rise to dout hold t doh c load = 20pf 13 ns sclk rise to dout valid t dov c load = 20pf 100 ns cs rise to dout disable t dod c load = 20pf; refer to figure 2 13 85 ns cs fall to dout enable t doe c load = 20pf; refer to figure 1 85 ns cs pulse-width high t csw 100 ns note 1: tested at v dd = v dd(min) . note 2: relative accuracy is the deviation of the analog value at an y code from its theoretical value after the full-scale range has b een calibrated. note 3: internal reference, offset, and reference errors nulled. note 4: conversion time is defined as the number of clock cycles multiplied by the cl ock period; clock has 50% duty cycle. note 5: external load should not change during conver sion for specified accuracy. guaranteed specification limit of 2mv/ma because of production test limitations. note 6: electrical characterist ics are guaranteed from v dd(min) to v dd(max) . for operations beyond this range, see typical operating characteristics. note 7: TSM1285 tested with 20pf on dout and f sclk = 4.8mhz, 0 to 3v. dout = full scale.
TSM1285 TSM1285 rev. 1.0 page 5 typical performance characteristics v dd = +3v ; f sclk = 4.8mhz ; c load = 20 p f ; 4.7 integral nonlinearity inl - lsb digital output code -0.4 -0.3 -0.2 -0.1 0 0.1 1k 2k 0 3k offset error vs supply voltage power supply voltage - volt offset error - lsb -0.2 -0.8 -1.4 -1.8 2.7 3.06 3.24 3.42 2.88 temperature - oc -15 35 60 85 10 -0.5 -1 -2 -1.5 1.2 0.8 0.6 -0.2 0.2 differential nonlinearity dnl - lsb digital output code 4k 5k 1k 2k 0 3k 4k 5k 0.2 0.3 0.4 -0.25 -0.2 -0.15 -0.1 0 0.2 0.25 -0.05 0.05 0.2 0.15 3.6 offset error - lsb offset error vs temperature -40 1 0.5 0 0.6 0.4 0.2 -0.2 0 gain error vs supply voltage power supply voltage - volt gain error - lsb gain error vs temperature temperature - oc -15 35 60 85 10 gain error - lsb -40 -0.4 -0.6 -1 -1.2 -1.6 2.7 3.06 3.24 3.42 2.88 3.6 1.2 1 0.8 1 0.4 0 -0.4
TSM1285 page 6 TSM1285 rev. 1.0 internal reference output vs supply voltage reference output - v power supply current vs power supply voltage power supply current vs temperature supply curent - ma 2.494 2.496 2.498 2.5 2.502 2.506 1.4 1.2 1 0.5 typical performance characteristics v dd = +3v ; f sclk = 4.8mhz ; c load = 20 p f ; 4.7 c load = 10pf converting sclk = 4.8mhz static 1.2 1.1 0.9 0.5 0.8 0.6 supply curent - ma static, v dd = 3v converting, v dd = 3v 2.504 internal reference output vs temperature reference output - v 2.498 2.5 2.502 2.504 2.506 2.510 2.508 2.7 3.06 3.24 3.42 2.88 3.6 1.3 1.1 0.7 0.9 1 0.7
TSM1285 TSM1285 rev. 1.0 page 7 pin functions pin name function 1 vdd power supply voltage, +2.7v to +3.6v. 2 ain analog signal input; unipolar, 0 to vref input range. 3 shdn active-low shutdown input. toggling shdn high-to-low powers down the TSM1285 and reduces the supply current to 2 a (typ). 4 ref reference voltage for analog-to-digital conversi on ? an internal 2.5v reference output. bypass with a good-quality 4.7 f capacitor. 5 gnd analog and digital ground. connect the TSM1285? s gnd pin at one and only one point to the system analog ground plane. 6 dout serial-data output. dout toggles state on sc lk?s rising edge and is high impedance when cs is logic high. 7 cs active-low chip select. the cs signal initiates the conversion process on its falling edge. when the cs input is logic high, dout is high impedance. 8 sclk serial-clock input. the sclk signal controls the conversion process and transfers output data at rates up to 4.8mhz. figure 1: output loading circuits for dout enable time (t doe ). figure 2: output loading circuits for dout disable time (t dod ).
TSM1285 page 8 TSM1285 rev. 1.0 description of operation converter operation the TSM1285 uses an input track-and-hold (t/h) and a successive-approximation r egister (sar) circuitry to convert an analog input signal to a digital 12-bit output. no external-hold capacitor is needed for the track/hold circuit. figure 3 illustrates the TSM1285 in its simplest configuratio n. the TSM1285 converts input signals within the 0v to v ref range in 3.3 s including the track-and-hold?s acquisition time. the serial interface requires only three digital lines (sclk, cs , and dout) and provides an easy interface to microprocessors ( ps) and microcontrollers ( cs). the TSM1285 has two operating modes: normal and shutdown. toggling (or driving) the shdn pin low shuts down the adcs and reduces supply current below 1 a when v dd 3.6v. open-circuiting or toggling (or driving) the shdn pin high or places the adcs into operational mode. toggling the cs pin to logic low initiates a conver sion where the conversion result is available at dout in unipolar serial format. the serial data stream consists of three leading zeros followed by the data bits with the msb first. all transitions on the dout pin occur within 20ns after the low-to-high transition of sclk. serial interface timing details of the TSM1285 are illustrated in figures 8 and 9. analog input figure 4 illustrates the sampling architecture of the analog-to-digital converter?s comparator. the full- scale input voltage is set by the TSM1285?s internal 2.5-v reference. track-and-hold operation during track mode, the analog signal is acquired and stored on the internal hold capacitor. during hold mode, the track/hold swit ches sw1 and sw2 are opened thereby maintaining a constant input level to the converter?s sar subcircuit. during the acquisition phase with sw1 and sw2 on track, the input capacitor, c hold , is charged to the analog input (ain). toggling the cs pin low causes the acquisition process to stop. at this instant, track/hold switches sw1 and sw2 are moved to hold position and the input side of c hold is then switched to gnd. unbalancing node zero at the comparator?s input, the retained charge on c hold represents a sample of the input signal applied to the converter. in hold mode and to restore node zero to 0v within the limits of the converter? s 12- bit resolution, the output of the capacitive digital-to-analog converter (the cdac) is adjusted during the remainder of the conversion cycle. in other words, the stored charge on c hold is transferred to the binary-weighted cdac where it is converted into a digital representation of the analog input signal. at end of the conversion figure 3: TSM1285 typical application circuit. figure 4: TSM1285 equivalent input circuit details.
TSM1285 TSM1285 rev. 1.0 page 9 process, the input side of c hold is switched back to ain so as to be charged to the input signal again. an adc?s acquisition time is function of how fast its input capacitance can be charged. if an input signal?s driving-point source impedance is high, the acquisition time is lengthened and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the adc requires to acquire the signal and is also the minimum time needed for the signal to be acquired. the TSM1285?s acquisition time is calc ulated from the following expression: t acq = 9 x (r s + r in ) x 10pf where r in = 100 ? (the TSM1285?s internal track/hold switch resistance), r s = the input signal?s source impedance, and t acq is never less than 625ns. because of the input structure of the TSM1285, sources with output impedances of 1k ? or less do not affect significantly the ac performance of the TSM1285. the TSM1285 can still be used in applications where the source impedance is higher so long as a 0.01 f capacitor is connected between the analog input and gnd. limiting the adc?s input signal bandwidth, the use of an external, input capacitor forms an rc filter with the input?s source impedance. input bandwidth considerations since the TSM1285?s input track-and-hold circuit exhibits a 10 mhz small-signal bandwidth, it is possible to measure periodic signals and to digitize high-speed transient events with signal bandwidths higher than the TSM1285?s sampling rate by using undersampling techniques. to avoid the aliasing of high-frequency signals into the frequency band of interest, the use of external anti-alias filter circuits (discrete or integrated) is recommended. the time constant of the external anti-alias filter should be set so as not to interfere with the desired signal bandwidth. analog input protection the TSM1285 incorporates internal protection diodes that clamp the analog input between v dd and gnd. these internal protection diodes allow the ain pin to swing from gnd - 0.3v to v dd + 0.3v without causing damage to the TSM1285. however, for accurate conversions near full scale, the input signal must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if the analog inputs can exceed 50mv beyond the supplies, then the current in the forward-biased protection diodes should be limited to less than 2ma since large fault currents can affect conversion results. internal reference considerations the TSM1285 has an internal voltage reference that is factory-trimmed to 2.5v. the internal reference output is connected to the ref pin and is also connected to the adc?s internal cdac. the ref output can be used as a reference voltage source for other components external to the adc and can source up to 750 a. to maintain conversion accuracy to within 1 lsb, a 4.7 f capacitor from the ref pin to gnd is recommended. while larger- valued capacitors can be used to further reduce reference wide-band noise, larger capacitor values can increase the TSM1285?s wake-up time when exiting from shutdown mode (see the ?using shdn to reduce operating supply current? section for more information). when in shutdown (that is, when shdn = 0), the TSM1285?s internal 2.5-v reference is disabled. serial digital interface initialization after powe r-up and starting a conversion if the shdn pin is not driven low upon an initial, cold- start condition, it may take up to 2.5ms for a fully- discharged 4.7 f reference bypass capacitor to provide adequate charge for specified conversion accuracy. as a result, conversions should not be initiated during this reference capacitor charge-up delay. to initiate a conversion, the cs pin is toggled (or driven) low. at the cs ?s falling edge, the TSM1285?s internal track-and-hold is placed in hold mode and a conversion is initiated. data can then be transferred out of the adc using an external serial clock.
TSM1285 page 10 TSM1285 rev. 1.0 figure 6: TSM1285 shutdown operation. using the adc?s shdn to reduce operating supply current power consumption can be reduced significantly by turning off the TSM1285 in between conversions. figure 5 illustrates the ts m1285?s average supply current versus conversion rate. the wake-up delay time (t wake ) is the time from when the shdn pin is deasserted to the time when a conversion may be initiated (refer to figure 6). this delay time depends on how long the adc was in shutdown (refer to figure 7) because the external 4.7 f reference bypass capacitor is discharged slowly when shdn = 0. timing and control details the cs and sclk digital inputs control the TSM1285?s conversion-start and data-read operations. the adc?s serial-interface operations are illustrated in figures 8 and 9. a cs high-to-low transition initiates the conversion sequence - the input track-and-hold samples the input signal level, the adc begins to convert, and the dout pin changes state from high impedance to logic low. the external sclk signal is used to drive the conversion process and is also used to transfer the converted data out of the adc as each bit of conversion is determined. the sclk signal transfers data after a low-to-high transition of the third (3 rd ) sclk pulse. after each subsequent sclk rising edge, transitions on the dout pin occur in 20ns. the third rising clock edge produces the msb of the conversion at dout, followed by the remaining bits. since there are twelve data bits and three leading zeros, at least fifteen rising clock edges are needed to transfer the entire data stream. extra sclk pulses occurring after the conversion result has been completely transferred out and, before to a new, low-to-high transition on cs , produce a string trailing zeros at dout. in addition, the extra sclk pulses have no effect on converter operation. minimum conversion cycle time can be accomplished by: (a) toggling the cs pin high after reading the conversion result?s lsb; and (b), after the specified minimum time defined by t cs has elapsed, toggling the cs pin low again to initiate the next conversion. output data coding and transfer function conversion results at the TSM1285?s dout pin are straight binary data. figure 10 illust rates the nominal transfer function where code transitions occur halfway between successive integer lsb values. if v ref = +2.500v, then 1 lsb = 610 v or 2.500v/4096. conversion rate - ksps supply curent - ma v dd = 3v dout = fs r l = c l = 10pf 100 10 1 0.1 0.1 1 100 1k 10 1k figure 5: TSM1285 supply current vs conversion rate
TSM1285 TSM1285 rev. 1.0 page 11 figure 8: TSM1285 serial interface timing sequence figure 9: TSM1285 serial interface timing specifications in detail. applications information connection to industry-standard serial interfaces the TSM1285?s serial interface is fully compatible with spi/qspi and microwire standard serial interfaces (refer to figure 11). for serial interface operation with these sta ndards, the cpu?s serial interface should be set to master mode so the cpu then generates the serial clock. second, the cpu?s serial clock should be c onfigured to operate up to 4.8mhz. the process to configure the serial clock and data transfer operation is as follows: 1) using a general-purpose i/o line from the cpu, the cs pin is driven low to start a conversion. dout transitions from high impedance to logic low. the sclk polarity should be low to start the conversion process correctly. 2) next, sclk is activated for a minimum of 15 sclk cycles where the first two sclks produce zeros at the dout pin. data at dout is formatted msb first and dout transitions occur 20ns after the third (3 rd ) sclk low-to-high transiti on. once the low-to-high sclk transition has occurred, data is valid at dout time in shutdown mode - sec reference power-up delay time - ms c ref = 4.7f 2 1 0.5 0 0.1m 10m 1 10 100m 2.5 1.5 1m figure 7: TSM1285 reference power-up delay vs duration in shutdown mode
TSM1285 page 12 TSM1285 rev. 1.0 according to the t dov (sclk rise to dout valid) timing specification. valid output data can then be transferred into p or cs on sclk low-to-high transitions. 3) at or after the 15th sclk low-to-high transition, the cs pin can be toggled high to halt the transfer process. if the cs pin remains low and the sclk is still active, trailing zeros ar e transferred out after the lsb. 4) once the cs pin is held at logic high for at least t cs , a new conversion cycle is started when the cs pin is toggled low. if a conversion is aborted by toggling the cs pin high before the current conversion has completed, a new conversion cycle can only be started after a the adc has acquired the signal (t acq ). the cs pin must be held low and sclk active until all data bits are transferred out of the adc. as shown in figure 8, data can be transferred in two 8-bit bytes or continuously. the bytes contain the result of the conversion padded with three leading 0s in the first 8- bit byte and 1 trailing 0 in the second 8-bit byte. spi and microwire interface details when using an spi or microwire interface, setting [cpol:cpha] = [0:0] configures the microcontroller?s serial clock and sampling edge for the TSM1285. the conversion commences on a high-to-low transition of the cs pin. the dout pin transitions from a high- impedance state to a logic low, indicating a conversion is in progress. two consecutive 1-byte data reads are required to transfer the full 12-bit result from the adc. dout output data transitions occur on the sclk?s low-to-high transition and are transferred into the downstream microcontroller on the sclk?s low-to-high transition. the first byte contains three leading 0s and then five bits of the conversion result. the second byte contains the remaining sev en bits of the conversion result and one trailing zero. re fer to figure 11 for the circuit connections and to figure 12 for all timing details. qspi details using a qspi microcontroller, setting [cpol:cpha] = [0:1] configures the microcontroller?s serial clock and sampling edge for the TSM1285. unlike the spi, which requires two 1-byte reads to transfer all 12 bits of data from the adc, the qspi allows a minimum number of clock cycles necessary to transfer data from the adc to the microcontroller. thus, the TSM1285 requires 15 sclk clock cycles from the microcontroller to transfer the 12 bits of data with no trailing zeros. as shown in figure 13, the conversion results contain two leading 0s followed by the msb-first-formatted, 12-bit data stream. figure 10: adc unipolar transfer function for straight binary digital data. figure 11: TSM1285 circuit connections to industry-standard serial interfaces.
TSM1285 TSM1285 rev. 1.0 page 13 figure 12: spi/microwire-TSM1285 serial interface timing details with [cpol:cpha] = [0:0]. figure 13 : qspi-TSM1285 serial interface timing details with [cpol:cpha] = [0:1]. pcb layout, ground plane management, and capacitive bypassing for best performance, printed circuit boards should always be used and wire-wrap boards are not recommended. good pc board layout techniques ensure that digital and analog signal lines are kept separate from each other, analog and digital (especially clock) lines are not routed parallel to one another, and high-speed digital lines are not routed underneath the adc package. a recommended system ground connection is illustrated in figure 14. a single-point analog ground (star ground point) should be created at the adc?s gnd and separate from the logic ground. all analog grounds as well as the adc?s gnd pin should be connected to the star ground. no other digital system ground should be connected to this ground. for lowest-noise operation, the ground return to the star ground?s power supply sh ould be low impedance and as short as possible. high-frequency noise on the v dd power supply may affect the adc?s high-speed comparator. therefore, it is necessary to bypass the v dd supply pin to the star ground with 0.1 f and 1 f capacitors in parallel and placed close to the adc?s pin 1. component lead lengths should be very short for optimal supply-noise rejection. if the power supply is very noisy, an optional 10- ? resistor can be used in conjunction with the bypass capacitors to fo rm a low-pass filter as shown in figure 14. figure 14: recommended power supply bypassing and star ground configuration.
TSM1285 page 14 silicon laboratories, inc. TSM1285 rev. 1.0 400 west cesar chavez, austin, tx 78701 +1 (512) 416-8500 ? www.silabs.com package outline drawing 8-pin soic package outline drawing (n.b., drawings are not to scale) patent notice silicon labs invests in research and development to help our custom ers differentiate in the market with innovative low-power, s mall size, analog-intensive mixed-signal solutions. s ilicon labs' extensive patent portfolio is a testament to our unique approach and wor ld-class engineering team. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laborat ories assumes no responsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, representation or guarantee regarding the suitability of its pr oducts for any particular purpose, nor does silicon laboratories assume any liability arising out of the application or use of any product or circ uit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intended to support or sustain life, or for any other application in wh ich the failure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. silicon laboratories and silicon labs are tr ademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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